1. Field of the Invention
The present invention relates to a semiconductor storage device and a cache memory. In particular, the invention relates to a semiconductor storage device capable of high-speed operation, and a cache memory including the same.
2. Description of Related Art
In recent years, there is an increasing demand to reduce a chip size of a semiconductor device such as a microcomputer with the aim of saving costs. In general, the microcomputer or the like includes a cache memory for temporarily storing data used in a processor. The cache memory is required to allow high-speed access even with a small capacity.
FIG. 6A shows a typical cache memory. In FIG. 6A, a cache memory 600 is connected with a processor 601 and an external memory, and includes a cache controller 610, a data RAM (Random Access Memory) 611, a valid bit memory 612 for storing Valid Bit, a dirty bit memory 613 for storing Dirty Bit, a tag memory 614, and a comparator 615.
A processor 601 processes data. The cache controller 610 controls data writing/reading between an external main memory and the cache memory 600. The data RAM 611 is a memory for storing the data proceed by the processor 601. The Valid Bit is one-bit data representing whether or not data stored in the data RAM 611 is valid. The valid bit memory 612 is a memory for storing the one-bit data. The Dirty Bit is one-bit data representing whether or not the data stored in the data RAM 611 is changed as a result of the processing of the processor 601. The dirty bit memory 613 is a memory for storing the one-bit data. A tag memory 614 is a memory for storing information about which address of the main memory corresponds to the data stored in the data RAM 611. A detailed description of the tag memory 614 is given below. The comparator 615 sends a signal representing the result of determining whether or not data is stored on the data RAM 611 based on the data received from the valid bit memory 612, the tag memory 614, and the processor 601 to the cache controller 610.
That is, the main memory has an address identifying a location of data, and address information is added to the data transferred from the main memory. In order for the processor 601 to process correct data, data on the cache memory 600 needs to match data on the main memory. The cache memory 600 checks whether or not data on the main memory matches data on the cache memory based on the address data, the Valid Bit, and the Dirty Bit. However, storing the information used for checking the data together with writing/reading data in the data RAM 611 hinders the efficient use of the data RAM 611 with a small capacity. To that end, the information used for checking the data is stored in the tag memory 614 specialized to an address data structure. The structure of the tag memory 614 is specialized to the address data structure, whereby the tag memory 614 enables higher access speed with a smaller footprint than the data RAM 611.
The cache memory 600 is connected with an external main memory through the cache controller 610. If the data RAM 611 has not stored same data as data with an address of the main memory which is required by the processor 601, the cache controller 610 outputs a Write Data signal for controlling data writing to the data RAM 611 to bring the data RAM 611 into a write enable state. After that, the cache controller 610 sends data (Cache Full Data) with the address of the main memory, which is required by the processor 601 to the data RAM 611 of the cache memory 600. In this way, the data on the main memory matches the data in the cache memory 600, a flag of the Valid Bit is set.
Further, if the data RAM 611 has stored data to be processed by the processor 601, the processor 601 executes processing using the data on the data RAM 611. The Dirty Bit is set in the cache memory 600 for determining whether or not data is changed as a result of the processing of the processor 601. If the data on the data RAM 611 is changed after being processed by the processor, a flag of the Dirty Bit is set. The cache controller 610 receives the changed data (Write Back Data) on the data RAM 611 based on the flag, and transfers the received data to the main memory.
When requiring data necessary for processing, the processor 601 sends address data for specifying an address of the requested data on the main memory. The address data sent from the processor includes tag address data and Index address data. The tag address data accounts for several upper bits of the address data. Further, the Index address data accounts for several lower bits of the address data. The tag memory 614 stores tag address data associated with the Index address data when a WriteTag signal as a write control signal from the cache controller 610 is at a write enable state. On the other hand, if the WriteTag signal from the cache controller 610 is at a write disable state, the tag memory 614 sends tag address data associated with the received Index address data.
The tag address data output from the tag memory 614 is input to the comparator 615. The comparator 615 sends a Hit signal if the tag address data from the tag memory 614 matches the tag address data from the processor 601, and the flag of the Valid Bit is set, that is, the data RAM 611 has stored objective data; otherwise, the comparator 615 sends a Miss Hit signal.
In summary, the cache memory 600 can instantly pass the data to the processor 601 if the data in the incorporated data RAM 611 matches the data on the main memory. The cache memory 600 and the processor 601 are mounted on the same semiconductor substrate or the cache memory 600 is connected with the processor 601 through a high-speed interface, so the processor 601 can access the cache memory 600 at an operating frequency higher than that of the external main memory. In other words, since frequently used data is stored in the cache memory 600, a processing speed of the entire system can be increased.
As a system of storing an address of data in the tag memory and controlling data on the data RAM in the cache memory, there are various systems such as a direct-mapped cache system and a set associative system. In any system, the tag memory functions to store tag address data and output the stored tag address data.
FIG. 6B shows a relation among the address data, the tag memory, and the data memory in accordance with the direct-mapped cache system. The address data sent from the processor includes tag address data and Index address data. The tag address data represents an address of an upper layer in the target address, for example, page number. The Index address data represents an address of a lower layer in the target address, for example, a line on the page specified by the tag address data. The tag memory 614 and the data RAM 611 includes as many memories as Index addresses. The Index address of the tag memory 614 is associated with the Index address of the data RAM 611.
When address data is sent from the processor 601, the tag memory 614 references the Index address data in the sent address data. The tag memory 614 output tag data corresponding to the referenced Index address data. After that, the tag address data of the address data sent from the processor 601 is compared with the tag address data read from the tag memory 614, and the Valid Bit associated with the Index address data is computed. As a result, if the tag address data on the tag memory 614 matches the tag address data from the processor 601, and the flag of the Valid Bit is set, a Hit signal is output. The cache memory 600 sends data corresponding to the Index address from the data RAM 611 based on the Hit signal.
An SRAM (Static RAM) or a memory using a flip flop is hitherto used as a typical tag memory. The SRAM used as the tag memory is described as the Related Art 1. Further, the memory having the flip flop as the tag memory is described as the Related Art 2.
FIG. 7A shows an SRAM 700a as the tag memory of the Related Art 1. The SRAM 700a of FIG. 7A is a circuit that receives the Index address data, the WriteTag signal, the tag address data, and clocks, and outputs tag data based on the received data and signal.
FIG. 8A is a timing chart of operations of the SRAM 700a as the tag memory of the Related Art 1. The SRAM 700a as the tag memory operates with a RAM's clock as an inverted a system clock in order to complete its operation with the system clock of one cycle.
First, an operation of writing the tag address data is described. If the WriteTag signal is at a write enable state, the SRAM 700a fetches a tag address at a timing T2 in step with a rising edge of the RAM's clock.
Next, an operation of reading the tag address data is described. If the WriteTag signal is at a write disable state, the SRAM 700a fetches tag address data in step with a rising edge of the RAM's clock at a timing T6, and outputs the data with a predetermined delay. Then, information about a result of comparing the tag address data from SRAM 700a with the tag data from the processor 601 is supplied to the cache controller 610 at a timing T7.
FIG. 7B shows a tag memory 700b using a flip flop of the Related Art 2. The tag memory 700b using a flip flop enables higher operating frequency than that of the SRAM 700a. Japanese Unexamined Patent Application Publication No. H10-335992 discloses an example of the flip flop.
The tag memory 700b using a flip flop of the Related Art 2 includes D-FFs (D-flip flops) 7100 to 710N (hereinafter collectively referred to as “D-FFs 710), AND gates 7200 to 720N (hereinafter collectively referred to as “AND gates 720”), a decoder 730, D latch n731, and a multiplexer 732.
The D-FFs 710 include an input terminal D, an output terminal Q, and a control terminal. The D-FFs 710 are circuits for storing data input to the input terminal D on the rising edge of a signal input to the control terminal as its output. In the Related Art 2, the signal input to the control terminal of the D-FFs 710 is a Masked clock signal controlled by the AND gates 720 that receive clock signals.
In the D-FFs 710, as many D-FFs as the number of bits of the stored tag address data are packaged into one cell, and plural cells are provided in a number corresponding to the number of Index address data. Each of the D-FFs 710 stores tag address data corresponding to the Index address data.
The AND gates 720 include first and second input terminals, and an output terminal. The AND gates 720 are circuits that output a signal of High level, provided that signals of High level (for instance, power supply potential) are input to both of the first and second input terminals; otherwise (when signals of High level are not input to both of the first and second input terminals), a signal of Low level (for instance, ground potential) is output.
The AND gates 720 are provided in a number corresponding to the number of D-FFs 710. The individual AND gates 720 are connected with a corresponding one of the D-FFs 710. A control signal is input to the first input terminal, and a clock is input to the second input terminal. That is, only the AND gates 720 designated by the control signal output a signal of High level in step with the clock. Thus, only the D-FFs 710 based on the Index address data are brought into a write enable state.
The decoder 730 receives Index address data that designates x-th Index address, and a WriteTag signal. The decoder 730 outputs a WETag [N:0] signal of (N+1) bit length for selecting the x-th D-FF 710 to which data is to be written, based on the thus-received address data and signal.
The D latch n731 includes an input terminal D, an output terminal Q, and a control terminal CLK. The D latch n731 is a circuit where a gate is opened to output a signal input to the input terminal D to the output terminal Q while an input voltage of the control terminal CLK is at the Low level. Further, while the input voltage of the control terminal CLK is at the High level, the gate is closed to keep the signal voltage level just before the input voltage of the control terminal CLK is turned to the High level.
The D latch n731 latches the input WETag [N:0] signal to generate an output signal based on the aforementioned operation. The latched signal becomes a control signal as a Latched WETag [N:0] signal of the (N+1) bit length, and is used for selecting the D-FF 710 to which data is written based on the Index address data.
The multiplexer 732 is a circuit for selecting a target D-FF from the D-FFs 710 based on the Index address data. The tag address data stored in the D-FFs 710 is output through the multiplexer 732. Thus, the tag address data stored in the target D-FF 710 is output based on the Index address data.
FIG. 8B is a timing chart of operations of the tag memory of the Related Art 2. First of all, an operation of writing the tag address data is described. In the tag memory 700b using a flip flop, the WETag [N:0] signal is generated between the periods during which the WriteTag signal is at a write enable state, based on the Index address data and the WriteTag signal in the period. As for the generated WETag [N:0] signal is determined by the D latch n731 during a period from the timing T2 to the timing T3, during which a clock is at a Low level. During the period from the timing T2 to the timing T4, the D latch n731 outputs the Latched WETag [N:0] signal. The Latched WETag [N:0] signal is used for selecting one from among the plural D-FFs 710. The selected D-FF 710 stores the tag address data fetched on the rising edge of the clock at the timing T3.
Next, an operation of reading the tag address data is explained. If the Index address data is changed, the tag memory 700b using a flip flop outputs the tag address data stored in the D-FF 710 designated by the Index address data.
In the case of using the tag memory 700b using a flip flop, since data reading can be started from the first half of a clock pulse, the tag memory 700b can use a system clock frequency higher than that of the SRAM 700a. 
The tag memory of the Related Art 1 or the Related Art 2 is hitherto used in the cache memory. However, if the SRAM 700a of the Related Art 1 is used for the tag memory 614, the rising edge of the RAM's clock is the falling edge of the clock, so the tag address data is output in the second half of the clock pulse. Moreover, the tag data cannot be output without a predetermined delay from the timing T6. In this case, the maximum clock operating frequency is limited to a value twice or more as long as the delay. That is, it is difficult to increase the operating frequency.
Further, in general, the tag memory 700b using a flip flop of the Related Art 2 increase a layout space for elements larger than the SRAM due to the flip flop. The larger layout space directly leads to an increase in chip cost, and hinders reduction in chip cost.
As discussed above, the conventional techniques have difficulties in realizing a semiconductor storage device that enables high-speed access with a small layout space.